Jean-Pierre Colinge received the Ph.D. degree in Applied Sciences
from the Université catholique de Louvain (UcL), Belgium, in 1984. He then
worked at the CNET, France, where he developed new silicon-on-insulator (SOI)
and 3D integration technologies. From 1985 to 1988, he worked at the Hewlett-Packard
Laboratories, Palo Alto, USA, where he was involved in thin-film SOI CMOS
research. From 1988 to 1991, he was with IMEC, Belgium, where he was involved
in SOI technology for VLSI and special device applications. From 1991 to 1997
he was professor at the UcL, working SOI technology for low-power, radiation-hard,
high-temperature and RF applications as well as low-dimensional devices. He
is now professor at the University of California. He has published over 250
scientific papers and three books on the field of SOI as well as two books
on semiconductor device physics.
- SOI Products
The advantages of SOI over bulk devices have been known for many years.
But it is only recently that high-quality SOI wafers have been made available
on an industrial scale. Once these wafers were available, it took only a
few years to witness the use of SOI microprocessors in personal computers
and SOI audio amplifiers in car stereo systems. Chances are the watch you
are wearing around your wrist has an SOI chip. This lecture covers the applications
of SOI in the areas of high-speed CMOS (microprocessors), memory chips,
low-voltage, low-power CMOS, mixed-mode circuits, and will briefly discuss
high-voltage and MEMS applications.
- Partially depleted MOSFETs
Partially depleted (PD) SOI MOSFETs have both advantages and drawbacks.
On one hand, floating substrate effects (kink effect, transient current
overshoots) increase the drain current, which increases the speed of PDSOI
circuits. On the other hand, floating body effects can create undesirable
effects, which if not accurately modeled, can hamper circuit operation.
These are single-transistor latch-up, snapback, parasitic bipolar effect,
history-dependent characteristics, etc. The use of body contacts can reduce
these problems. One-transistor memory cells based on floating-body effects
have been proposed.
- Low- and high-temperature operation
SOI MOSFETs have lower leakage currents than bulk devices at high temperature,
as well as a smaller variation of threshold voltage with temperature. They
are also immune to temperature-induced latchup. As a result, SOI circuits
can operate at temperatures above 300șC, while bulk CMOS is usually limited
to 150șC. Low-temperature operation improves mobility and subthreshold slope,
but, more importantly, opens the possibility of exploring quantum effects.
Subband splitting can be observed in two- and one-dimensional SOI devices,
and single-electron transistors operation is made possible.
General information on Books
on SOI, SOI news, etc.: http://www.soisolutions.com/
Fully Depleted SOI MOSFETs
Electrical Characterization of Silicon-on-Insulator Materials
and Devices: http://www.wkap.nl/prod/b/0-7923-9548-4
SOI Circuit Design Concepts: http://www.wkap.nl/prod/b/0-7923-7762-1
CMOS VLSI Engineering: Silicon-on-Insulator (SOI): http://www.wkap.nl/prod/b/0-7923-8272-2
SOI Design: Analog, Memory and Digital Techniques: http://www.soidesign.info/overview.htm
Silicon-on-Insulator Technology: Materials to VLSI, 3rd
"Low temperature electronics: from fundamental physics to emerging
silicon technologies", C. Claeys and E. Simoen, Electrochemical Society
Proceedings, Vol. 2003-09, Ed. by. J.A. Martino, M.A. Pavanello and N. I.
Morimoto, pp. 96-11, 2003;
Device and Circuit Cryogenic
Operation for Low Temperature Electronics: http://www.wkap.nl/prod/b/0-7923-7377-4