Sunday
27 june
Monday
28 june
Tuesday
29 june
Wednesday
30 june
Thursday
1 july
Friday
2 july
8h30
G. Celler
Introduction
What is SOI ?
Y. Cayrefourq
C.Mazuré

SOI materials - Smartcut :
unibond  and beyond
J. Fossum
Fully depleted MOSFETs (2)
D. Ioannou
Advanced characterization
D. Ioannou
Reliability of SOI devices
T. Skotnicki
Ultimate scaling
9h30
J.-P. Colinge (1)
SOI Products
S. Bengtsson
Other SOI materials
E. Sangiorgi
Advanced Modeling & Simulation (1)
J. Fossum
Double-gate & advanced MOSFETs
J.-P. Colinge
Low & High temperature operation
M. Mouis
Strained Si on SOI
10h30
Break
Break
Break
Break
Break
Break
11h
A. Vandooren
Technology modules
J-P.Colinge
Partially depleted
MOSFETs (1)
S. Cristoloveanu
Material Characterization
B. Redman-White
Design for SOI
analog circuit design
L. Risch
FINFET
J.-M. Fournier
Design for SOI-RF circuits
M. Sanquer
Emerging quantum & tunneling devices
12h30
Lunch
Lunch
Lunch
Lunch
Lunch
Lunch
-15h
Social
Program
Bus departure at 3 pm
16h30
Ch. Maleville
Material Characterization
J-P.Colinge
Partially depleted
MOSFETs (2)
E. Sangiorgi
Advanced Modeling & Simulation (2)
FAB VISIT :
SOITEC/Crolles
J.-L. Pelloie
Design for digital SOI
J.-L. Pelloie
LP/LV SOI circuits
 
18h Break Break Break   Break Break
18h15   J. Fossum
Fully depleted MOSFETs (1)
S. Cristoloveanu
Electrical Characterization
Visit or shopping
in Grenoble
S. Renard
MEMS
 
19h30
Diner
Diner
Poster Session ans Drinks
Gala Dinner at 8 pm Grenoble
Diner
Diner
 
 
Scientific Program
 

Biographies of lecturers
George Celler Dimitris Ioannou
Jean-Pierre Colinge Bill Redman-White
Anne Vandooren Jean-Luc Pelloie
Yan Caeyrefourcq Jean-Michel Fournier
Stefan Bengtsson Jean-Luc Pelloie
Sorin Cristoloveanu Stéphane Renard
Christophe Maleville Thomas Skotnicki
Jerry Fossum Mireille Mouis
Lothar Risch Marc Sanquer
Enrico Sangiorgi    
   

Dr. George Celler

Dr. George Celler is Chief Scientist at SOITEC/USA. Previously, he spent 25 years at Bell Laboratories in Murray Hill, New Jersey, where he was a Distinguished Member of Technical Staff and Technical Manager. He received his M.Sc. degree from the University of Warsaw and a Ph.D. in solid state physics from Purdue University. In addition to his long-term interest in silicon-on-insulator structures and their applications, he also investigated laser annealing and rapid thermal processing of semiconductors, diffusion phenomena in Si and silicon dioxide, and x-ray lithography. He published over 170 articles, edited seven books, and was issued 15 US patents. He is a fellow of the American Physical Society and of The Electrochemical Society, a member of IEEE and the Materials Research Society. He has received the 1994 Electronics Division Award of The Electrochemical Society, and two Bell Labs President's Gold Awards.

 

Jean-Pierre Colinge

Jean-Pierre Colinge received the Ph.D. degree in Applied Sciences from the Université catholique de Louvain (UcL), Belgium, in 1984. He then worked at the CNET, France, where he developed new silicon-on-insulator (SOI) and 3D integration technologies. From 1985 to 1988, he worked at the Hewlett-Packard Laboratories, Palo Alto, USA, where he was involved in thin-film SOI CMOS research. From 1988 to 1991, he was with IMEC, Belgium, where he was involved in SOI technology for VLSI and special device applications. From 1991 to 1997 he was professor at the UcL, working SOI technology for low-power, radiation-hard, high-temperature and RF applications as well as low-dimensional devices. He is now professor at the University of California. He has published over 250 scientific papers and three books on the field of SOI as well as two books on semiconductor device physics.

 

Anne Vandooren

Anne Vandooren was born in Belgium. She received the Electrical Engineer bachelor degree from the Universite catholique de Louvain (UCL) in Belgium in 1996 and the Ph.D degree in Electrical Engineering from the University of California, Davis in 2000. She received the best dissertation award in electrical engineering from UCDavis. In 2000, she joined Motorola, Digital DNA laboratories in Austin, Texas. Her areas of interest include Silicon-On-Insulator technology and novel structures for sub-nanometer technologies. She has published over 10 journal papers and over 25 conference papers in the field of SOI technology.

 

Dr Ian Cayrefourcq

Dr Ian Cayrefourcq joined Soitec in 2002 , he is currently the New Technology Development Department Manager. Previously, he worked 4 years at Thales as R&D engineer in optoelectronics. Then, in 1998, he joined Corning Inc. as project leader in charge of developing Dynamic Gain Flattening Filters. He received an engineering degree in Material Science, a Master degree in Solid State Physics and a PhD in Microelectronics from IEMN (Institute of Electronics and Microelectronics of northern France). He owns more than 10 patents and authored or co-authored more than 20 publications relative to SOI.

 

Stefan Bengtsson

Stefan Bengtsson received the MSc degree in Engineering Physics from Chalmers University of Technology in 1985. Before going back to university for a PhD exam, he worked with SAAB Automobile in Trollhättan, Sweden. He obtained his PhD in 1992 in Solid State Electronics at Chalmers University. Presently he is Professor in Solid State Electronics and Head of the Department of Microtechnology and Nanoscience (MC2) at Chalmers. His main research interests are in the fields of SOI, wafer bonding and MOS technology. Recently he has also been involved in projects aiming at integrate molecular electronics and silicon for future microelectronics. Stefan Bengtsson is author or co-author of around 50 scientific journal papers and around 70 contributions to international conferences.

 

Sorin Cristoloveanu

Sorin Cristoloveanu received the PhD (1976) in Electronics and the French Doctorat ès-Sciences in physics (1981) from the National Polytechnic Institute, Grenoble (INPG), France. He joined the Centre National de la Recherche Scientifique (CNRS) and became a Senior Scientist in 1982 and a Director of Research in 1989. In 1989, he joined the University of Maryland, College Park, as an Associate Professor for one sabbatical year. He also worked at JPL (Pasadena), Motorola (Phoenix), and the Universities of Florida (Gainesville) and Nashville. From 1993 to 1999, he served as the director of the LPCS Laboratory of INPG. Between 1999-2000, he was in charge of the creation of the Center for Advanced Projects in Microelectronics (CPMA Grenoble). He is the author or co-author of more than 400 technical journal papers and communications at international conferences (including 80 invited contributions). He is the author or the editor of 13 books, and he has organized 9 international conferences. His expertise is in the area of the electrical characterization and modeling of semiconductor materials and devices, with special interest for silicon-on-insulator structures. With his students, he has received 5 Best Paper Awards, an Academy of Science Award (1995), and the Electronics Division Award of the Electrochemical Society (2002). He is a Fellow of IEEE, a Fellow of the Electrochemical Society, and Editor of Solid-State Electronics.

 

Christophe Maleville

Christophe Maleville, PhD, is process engineering manager at Soitec (Bernin, France). Since 1993 he has been involved with the development of the Smart Cut process in collaboration with Commissariat à l'Energie Atomique/Laboratoire d'Electronique de Technologie d'Information (CEA/LETI) and has worked on its application to the manufacturing of SOI wafers. Currently he participates in new SOI process development and in transferring SOI technology to production. He has authored or coauthored more than 30 papers dealing with SOI manufacturing and metrology and holds approximately 15 patents in that area. He received a PhD in microelectronics from the Institut Polytechnique de Grenoble.

 

Jerry G. Fossum

Jerry G. FOSSUM was born in Phoenix, AZ (U.S.A.) He received the B.S., M.S., and Ph.D. degrees in electrical engineering from the University of Arizona, Tucson, after which, in1971, he joined the technical staff of Sandia Laboratories, Albuquerque, NM. In 1978 he moved to the University of Florida, Gainesville, where he is now Professor of Electrical and Computer Engineering. His general area of interest is semiconductor device theory, modeling, and design; his current research concerns physical, process-based device modeling for IC simulation and technology CAD, with emphasis on nonclassical SOI and multi-gate CMOS. He is the author or coauthor of more than 200 papers published in technical journals and conference proceedings, and he has directed the research of 30 Ph.D. students. In 1983 he was elected a Fellow of the IEEE for "contributions to the theory and technology of silicon solar cells and transistors.

 

Lothar Risch

Lothar Risch received the diploma degree in physics from the Technical University of Berlin in 1974 and the doctor degree from the Technical University of Karlsruhe in 1976. He joined Siemens Corporate Research in Munich in 1977. Since then, he has been engaged in Silicon microelectronics with Charge Coupled Devices, DRAM memory cell development from 4 to 256 Mbit, CMOS logic , and Nanoelectronics. In 1999 he moved to Infineon Technologies, the former Siemens Semiconductor Group. Now, he is a senior director of the department Corporate Research Nanodevices with the main acivity on 50 to 10nm CMOS. He filed more than 50 patents/ applications and is author/coauthor of more than hundred papers. He is also a member of several advisory boards and of the technical program committees of ESSDERC, IEDM, ULIS and ULSI.
Lothar Risch / Infineon Technologies - Münich - Germany

 


Enrico Sangiorgi

Enrico Sangiorgi received the Laurea degree in Electrical Engineering from the University of Bologna, Italy, in 1979. In 1993 he has been appointed Full Professor of Electronics at the University of Udine, Italy, where he started the Electrical Engineering Program and the Microelectronic group. In 2002 he joined the University of Bologna and the Center of Excellence ARCES. From 1985 to 2001 he has been a consultant of Bell Laboratories - Lucent Technologies, Murray Hill, New Jersey, where he has been a Resident Visitor for more than three years. In 1983, 1984, and 1991 he was a Visiting Scientist at Center for Integrated Systems, Stanford University, California. Since 1994 he is Editor of the IEEE Electron Device Letters. He has been a member of the Technical Committees of several International Conferences on Electron Devices: IEDM, ESSDERC, INFOS, ULIS, etc. Enrico Sangiorgi coauthored 29 IEDM papers and overall more than 140 papers on international journals and conference proceedings with referee.

 


Dimitris E. Ioannou

Dimitris E. Ioannou received his B.Sc. in Physics (1974), from Thessaloniki University, Greece and his MSc. (1975) and Ph.D. (1978) in Solid-State Electronics, from Manchester University, UK. Prior to his current position of professor of electrical and computer engineering at George Mason University (Fairfax, VA), he has held positions at Manchester and Middlesex Universities (UK), Democritus University of Thrace (Greece), and University of Maryland (College Park), and spent Spring of 2001 on sabbatical leave at ENSERG (France). His has developed SEM-EBIC techniques for characterizing electrically active defects and measuring the diffusion length, and techniques for studying deep traps, carrier lifetime and interface states in SOI. He has studied the physics and hot carrier reliability of SOI devices, including the opposite-channel based carrier-injection and a SOI flash memory cell. He developed Schottky and Ohmic contact technology for SiC. His current research interests are on performance and reliability issues of SOI and bulk CMOS devices and circuits. He has authored or coauthored over a hundred research papers, and was the advisor of more than twenty research students. He has been actively involved with the annual IEEE International SOI Conference for over fifteen years, most recently as technical program chairman (SOI'2001) and general chairman (SOI'2002).

 

William Redman-White

William Redman-White obtained the B.Sc. degree from Exeter University in 1974, and M.Sc and PhD degrees from Southampton University in 1980 and 1983 respectively. From 1974 to 1978 he was with Post Office Telecommunications, working on PCM systems, and joined the academic staff of Southampton University in 1983. Whilst maintaining a continuing academic activity, Dr Redman-White has worked extensively in the semiconductor industry. From 1984 to 1990 he was part-time design consultant for GEC Research (London) working on Silicon-on-Sapphire design amongst other things, and during 1989 he was full-time with Motorola, Switzerland. Since 1990, he has been over half-time with Philips Semiconductors, in Southampton, Caen (France) and from 2001-2003 in San Jose (USA). Presently with the position of Fellow, he undertakes advanced development work in consumer and RF projects. His research is centred on mainstream analogue and RF design issues, with an interest in SOI CMOS characterisation, modelling and design for space environments. He has served as an associate editor of the Journal of Solid State Circuits, and is a member of the IEE and of the IEEE.

 

Jean-Luc Pelloie

Jean-Luc Pelloie co-founded the SOISIC (Silicon On Insulator Systems and Integrated Circuits) company in April 2001, a unique independent company providing IP blocks (standard cell and I/O libraries, SRAM, analog and RF blocks) and addressing SOI circuit design, from Spice modeling to ASIC design. He obtained his PhD degree in Electronics from the INSA de Lyon in 1984. He joined LETI, a french R&D laboratory from the Commissariat à l'Energie Atomique (CEA) in 1986. After being involved in the development and characterization of bulk CMOS technologies, he managed the development of CMOS/SOI technologies for more than 10 years. Jean-Luc Pelloie developed the LETISOI model for SPICE simulation of SOI circuits. He has authored and co-authored more than 100 papers and deposited 3 patents, being invited in several international conferences (SOI conference, ISSCC, ESSDERC, SEMI).

 

Jean-Michel Fournier

Jean-Michel Fournier graduated in Electronic engineering from the National Engineer School (ENSEEIHT), Toulouse, in 1974. He received the M.S and PhD degrees from the department of Solid-State Physic, University Claude Bernard, Lyon, in 1975 and 1979 respectively. In 1979, he joined the R&D in Microelectronic Department of France Telecom, Grenoble, where he worked on analog MOS ASIC development (High speed video amplifiers, Gmc filters, device modeling). Between 1992 and 1996, he was in charge of the analog design group, and he focused his interest on BiCMOS process for RF applications. From 1996, he is a professor at ENSERG (Electronic Engineering School of INPG). At IMEP laboratory, his main research interest is in the design of analog RF circuits in CMOS/SOI technology with collaboration with ST Microelectronics, Crolles.

 

Stéphane Renard

Stéphane Renard was born in Nice in 1956. He graduated from the Ecole Centale in Paris in 1979 and received his Ph.D. in Applied Physics (Optoelectronics) in 1983 from Institut National Polytechnique de Grenoble for a research study about Detector arrays dedicated to an Integrated Optics Spectrum Analyser. In 1983, he joined LETI (CEA) where he participated to various R&D projects and technology transfers in optoelectronics: Flat Panel Display, Integrated Optics, Magneto-Optics and Optical Sensors. From 1993 to 1997, he was the LETI micro-sensors R&D team manager before creating in May 1997, TRONIC'S Microsystems for which he has been, since then, the Executive Chairman.
Tronic's Microsystems is a spin-off of CEA-LETI created in May 1997. It is one of the most experienced contract manufacturers of silicon-based MEMS (Micro-Electro-Mechanical Systems), expert in surface and bulk micromachining of SOI and silicon

 

Thomas Skotnicki

Thomas SKOTNICKI (PhD and HDR-Habilité à Diriger des Recherches) is the Advanced Devices Program Manager in STMicroelectronics (Crolles, France) responsible for the R&D projects of ST and of the Crolles Alliance (ST, Philips, Motorola) on 45nm and beyond FE CMOS modules, on innovative device architectures, new memory concepts and cells, and integration of new materials for CMOS. He has been active in the ITRS work towards development of CMOS Roadmaps 2001 and 2003 and of the NonClassical CMOS Roadmap. He has had responsibilities in numerous European CMOS technological projects (NOVA, ACE, MEDEA, HUNT, etc), holds 50 patents and has authored a number of invited plenary talks/ short course lectures (Symp On VLSI Technology, SSDM, ESSDERC, ECS Symposia, SOI-Conference, ELTE, SEMICON, IWJT, USJ-Conf, SOITEC Workshop on SOI, MNE, etc.) and over 100 specific papers in the field of CMOS devices and circuits. He also authored 2 chapters for the French Encyclopedia TI (Techniques de l'Ingénieur), and 5 book chapters on new device structures, CMOS roadmap, and advanced technology. He was a member of Program Committees for IEDM 1997-98, and the SSD Subcommittee chairman for IEDM 2003, and is currently the EU representative for the IEDM Executive Committee 2004 and 2005. He is a co-recipient of the Paul Rappaport Award for the best IEEE EDS paper (on SON -Silicon-On-Nothing technology) of year 2000, and of the ESSDERC 2000 Best Paper (on "dielectric pockets") Award. Since May 2001 he has been serving as co-Editor for IEEE TED in the field of MOS Devices and Technology. In 1998 he was elected a Senior Member of the SEE (French Société des Electriciens et des Electroniciens) for outstanding achievements in the field of electricity and electronics. In 2001 he was elected a Senior Member of the IEEE.

 


Mireille Mouis

Mireille Mouis graduated from the ENS Cachan and received the Applied Physics Agrégation in 1980. She obtained the Thèse de 3eme cycle degree in 1982 and the Doctorat d'Etat degree in 1988, both from Paris XI University. She joined CNRS in 1985 at the Institut d'Electronique Fondamentale (IEF) in Orsay, where she was working on Monte-Carlo simulation of III-V heterojunction FETs and transport in a 2D electron gas at short gate length. From 1992 to 2000, she contributed to the development of a CMOS integrated SiGe HBT technology at CNET Meylan and to its transfer to STMicroelectronics. She is presently coordinating a research group on novel CMOS-compatible architectures at the Institute of Microelectronics, Electromagnetism and Photonics (IMEP) in Grenoble. Her research interests concern operation of advanced microelectronics devices (strained channels, SOI and multiple gate structures, quantum devices…) in the context of CMOS integration.

 


Marc Sanquer

Marc Sanquer is graduated from the Ecole Polytechnique, France. He received the PhD degree in physics from the Paris-sud-Orsay university, France in 1985. In 1985 he joined the Atomic Energy Council (CEA) as a research scientist in Saclay, France, working on mesoscopic quantum physics since 1988. In 1996 he joined the department for basic research in condensed matter at the CEA-Grenoble, France, where he is currently in charge of the quantum mesoscopic physics, involved in ultimate silicon devices. His current interests are the electronic correlations -including Coulomb blockade- and interferences effects in quantum electronic systems. Dr. Marc Sanquer is co-author of more than 70 scientific publications.