Scientific Chair:
Sorin Cristoloveanu, IMEP-Grenoble

Introduction to SOI
What is SOI ? Do we really need it ?

George Celler, SOITEC, USA
SOI products: μ-processors, LP/LV, RF, high voltage, MEMS & sensors, etc
Jean-Pierre Colinge, Univ. of California, USA
Technology modules
Anne Vandooren, Motorola, France

SOI Materials
Smart-Cut: Unibond and beyond
Yan Caeyrefourcq, SOITEC, France
Other SOI materials
Stefan Bengtsson, Chalmers Univ., Sweden
Material characterization - Electrical techniques - other techniques
Sorin Cristoloveanu, IMEP, France
Christophe Maleville, SOITEC, France

SOI Transistors operation, physics mechanisms & models, simulations
Typical mechanisms in partially depleted MOSFETs
Jean-Pierre Colinge, Univ. California, USA
Typical mechanisms in fully depleted MOSFETs
Jerry Fossum, Univ. Florida, USA
Mechanisms in double-gate and other advanced MOSFETs: FinFET + Vertical
Other mechanisms and devices

Lothar Risch, Infineon, Germany
Jerry Fossum, Univ. of Florida, USA
Advanced modeling & simulation
Enrico Sangiorgi, Univ. of Bologna, Italy

Electrical Characterization and Reliability
Basic methods for routine evaluation
Sorin Cristoloveanu, IMEP, France
Advanced techniques for detailed characterisation
Dimitris. Ioannou, George Mason Univ., USA
Reliability of SOI devices (hot carriers, radiation, etc)
Dimitris Ioannou, George Mason Univ., USA
Low and high temperature operation
Jean-Pierre Colinge, Univ. of California, USA

Designing SOI Circuits
Design principles of SOI analog circuits
Bill Redman-White, Univ. of Southampton, UK
Design principles for digital SOI circuits
Jean-Luc Pelloie, SOISIC, France
RF circuit design
Jean-Michel Fournier, IMEP, France
Low-power & low-voltage SOI circuits
Jean-Luc Pelloie, SOISIC, France

From Micro to Nano SOI
SOI Microsystems & MEMS
Stéphane Renard, Tronics Microsystems, France
Ultimate scaling of SOI MOSFETs
Thomas Skotnicki, STMicroelectronics, France
Strained Si on SOI MOSFETs
Mireille Mouis, IMEP, France
Quantum effects in SOI devices
Marc Sanquer, CEA, France

 

 

 

 

What is SOI? Do we really need it?

This introductory lecture will identify basic ideas and concepts associated with SOI materials, devices, and applications. These concepts will be developed and explained in much more detail by other speakers later in the week. CMOS, bipolar, RF CMOS, high voltage and smart power circuits, systems-on-a chip (SOCs) - they can all benefit from being built on SOI wafers. So do many MEMS structures and microphotonic circuits. The field of SOI was first driven by the need for radiation-hardened electronics. Currently, enhanced performance - increased switching speed and reduced power consumption - are the prime reasons for utilizing SOI, while reduction of short channel effects will soon be the dominant factor. Developing high quality single crystalline Si on insulator has a long and interesting history. Some early attempts to form SOI structures will be mentioned. Out of the confusion of numerous competing approaches, current high volume manufacturing methods have emerged. SOI technology has moved into the mainstream of microelectronics, and many users of personal computers, computer servers, and consumer electronics do not even realize that SOI chips drive their systems.

Recommended Readings
1. G. K. Celler and Sorin Cristoloveanu, «Frontiers of silicon-on-insulator», J Appl. Phys. Vol. 93, pp.4955-4978 (May 1 2002).
2. G. Dan Hutcheson, «The first nanochips», Scientific American, April 2004, pp.76-83.
3. A. Liu et al., «A high speed optical modulator....», nature Vol 427, pp.615-618 (Feb 12, 2004)
4. C.-T. Chuang et al., «Scaling planar silicon devices», IEEE Circuits and Devices Vol 20, (1), pp. 6-19 (Jan. 2004)
5 E. J. Nowak et al., «Turning silicon on its edge», IEEE Circuits and Devices Vol 20, (1), pp. 20-31 (Jan. 2004)
6. «Wafer Bonding, Applications and Technology» M. Alexe and U Goesele, eds. (Springer 2004).

SOI Products

The advantages of SOI over bulk devices have been known for many years. But it is only recently that high-quality SOI wafers have been made available on an industrial scale. Once these wafers were available, it took only a few years to witness the use of SOI microprocessors in personal computers and SOI audio amplifiers in car stereo systems. Chances are the watch you are wearing around your wrist has an SOI chip. This lecture covers the applications of SOI in the areas of high-speed CMOS (microprocessors), memory chips, low-voltage, low-power CMOS, mixed-mode circuits, and will briefly discuss high-voltage and MEMS applications.

Recommended Readings
General information on Books on SOI, SOI news, etc.: http://www.soisolutions.com/
SOI Products:
http://www.soisolutions.com/news.html
http://www.soisolutions.com/archive.html

Technology modules

This lecture will review the major modules used for process integration of SOI devices, including single-gate PDSOI or FDSOI devices or even double (or multiple) -gate transistors. The technical challenges faced by each of these different modules will presented. These modules will include isolation, substrate engineering (limits of ultra-thin layers, strained layers, buried insulator materials,...), gate stack ( high k and workfunction engineering technique) and methods for reducing SD parasitic resistance, such as elevated source/drain. The impact of each of these modules on performance and manufacturability will be discussed.

Smart CutTM : Unibond and Beyond

In this paper, we will review the SOI roadmap going through the newest development in SOI material. This will include Ultra-Thin SOI as well as strained SOI (sSOI) or GeOI. After having presented their applications, we will review the technical specificities of each of these engineered substrates and explain how they participate in the continuous enhancement of the devices performances. A specific attention will be put on the metrology challenges that we will need to face with such new material.

Other Soi materials

In this lecture the history of SOI-materials will be covered. The different types of SOI-materials, their manufacturing processes and specific peculiarities will be described. The lecture will cover the main type of materials that have been added to the «SOI-family» through the years: SOS and other heteroepitaxial materials, ELO, FIPOS, re-crystallized materials, DI-materials, SIMOX and BESOI all the way up to but not including the smartcut technique and the Unibond material. Smartcut and Unibond will be covered in the separate lecture by Carlos Mazuré.

Recommended Readings
Electrical Characterization of Silicon-on-Insulator Materials and Devices:
http://www.wkap.nl/prod/b/0-7923-9548-4
Silicon-on-Insulator Technology: Materials to VLSI, 3rd Edition:
http://www.wkap.nl/prod/b/1-4020-7773-4
P.F.L Hemment: The SOI odyssey, Electrochemical Society Proceedings, vol 2003-05, p.1

Electrical characterization of SOI materials and devices

The key methods used for the electrical evaluation of SOI material and device properties are reviewed in terms of physics-based principles, experimental set-up and parameter extraction techniques. The Pseudo-MOSFET is a surprising and efficient method, which works only in SOI wafers and provides straightforward information on the quality of the thin silicon film, buried oxide and interface. The Pseudo-MOSFET secrets and variants are addressed. We discuss the properties of various SOI wafers by focusing on the impact of film thinning on the carrier mobility and generated defects. Other characterization methods at the wafer level (Van der Pauw, capacitance, etc) are briefly described. The second section of the course is dedicated to MOS device characterization. The basic techniques (static I(V) curves in MOSFETs, gated-diode current, charge pumping, transient currents, etc) are discussed by showing the difference between fully and partially depleted structures. The relevant models and strategies enabling to extract the material and technology properties from device-based measurements will be documented.

Partially depleted MOSFETs

Partially depleted (PD) SOI MOSFETs have both advantages and drawbacks. On one hand, floating substrate effects (kink effect, transient current overshoots) increase the drain current, which increases the speed of PDSOI circuits. On the other hand, floating body effects can create undesirable effects, which if not accurately modeled, can hamper circuit operation. These are single-transistor latch-up, snapback, parasitic bipolar effect, history-dependent characteristics, etc. The use of body contacts can reduce these problems. One-transistor memory cells based on floating-body effects have been proposed.

Fully Depleted SOI MOSFETs - Basic Properties

The basic properties of fully depleted (FD) SOI MOSFETs, due in large part to the gate-substrate charge coupling enabled by the FD/SOI body, are overviewed. The coupling defines a threshold voltage that is dependent on the substrate, or back-gate bias, but is independent of the (applied or induced) body bias, meaning no floating-body effects (with the exception of those defined by the parasitic lateral BJT). For long channel lengths and relatively thick buried oxide (BOX), the coupling underlies near-ideal device characteristics, such as low subthreshold gate swing, high drain saturation current, and small weak/moderate-inversion gate capacitance. However, for short channel lengths, the near-ideal characteristics can be undermined because of lateral electric-field fringing in the BOX and carrier-velocity saturation in the channel, as well as short-channel effects in the SOI body and possibly depletion-charge neutralization in the body if it is highly doped.

Recommended Readings
Recommended Readings
- Jerry G. Fossum SOI Group Website : http://www.soi.tec.ufl.edu
- H.-K. Lim and J. G. Fossum, “Threshold Voltage of Thin-Film Silicon-on-Insulator (SOI) MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-30, pp. 1244-1251, Oct. 1983.
- S. Veeraraghavan and J. G. Fossum, “A Physical Short-Channel Model for the Thin-Film SOI MOSFET Applicable to Device and Circuit CAD,” IEEE Trans. Electron Devices, vol. 35, pp. 1866-1875, Nov. 1988.
- J.-Y. Choi and J. G. Fossum, “Analysis and Control of Floating-Body Bipolar Effects in Fully Depleted Submicrometer SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 38, pp. 1384-1391, June 1991.
- J. G. Fossum and S. Krishnan, “Current Drive Enhancement Limited by Carrier Velocity Saturation in Deep-Submicrometer Fully Depleted SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 40, pp. 457-459, Feb. 1993.
- P. C. Yeh and J. G. Fossum, “Physical Subthreshold MOSFET Modeling Applied to Viable Design of Deep-Submicrometer Fully Depleted SOI Low-Voltage CMOS Technology,” IEEE Trans. Electron Devices, vol. 42, pp. 1605-1613, Sept. 1995.
- J. G. Fossum, S. Krishnan, O. Faynot, S. Cristoloveanu, and C. Raynaud, “Subthreshold Kinks in Fully Depleted SOI MOSFET’s,” IEEE Electron Device Lett., vol. 16, pp. 542-544, Dec. 1995.
- S. Krishnan and J. G. Fossum, “Compact Non-Local Modeling of Impact Ionization in SOI MOSFET’s for Optimal CMOS Device/Circuit Design,” Solid-State Electron., vol. 39, pp. 661-668, May 1996.
- M. M. Pelella, J. G. Fossum, D. Suh, S. Krishnan, K. A. Jenkins, and M. J. Hargrove, “Low-Voltage Transient Bipolar Effect Induced by Dynamic Floating-Body Charging in PD/SOI MOSFET’s,” IEEE Electron Device Lett., vol. 17, pp. 196-198, May 1996.
- J. G. Fossum, K. Kim, and Y. Chong, «Extremely Scaled Double-Gate CMOS Performance Projections, Including GIDL-Controlled Off-State Current,» IEEE Trans. Electron Devices, vol. 46, pp. 2195-2200, Nov. 1999.
- K. Kim and J. G. Fossum, “Double-Gate CMOS: Symmetrical- versus Asymmetrical-Gate Devices,” IEEE Trans. Electron Devices, vol. 48, pp. 294-299, Feb. 2001.
- L. Ge, J. G. Fossum, and B. Liu, “Physical Compact Modeling and Analysis of Velocity Overshoot in Extremely Scaled CMOS Devices and Circuits,” IEEE Trans. Electron Devices, vol. 48, pp. 2074- 2080, Sept. 2001.
- L. Ge and J. G. Fossum, “Analytical Modeling of Quantization and Volume Inversion in Thin Si-Film Double-Gate MOSFETs,” IEEE Trans. Electron Devices, vol. 49, pp. 287-294, Feb. 2002.
- J. G. Fossum, L. Ge, and M.-H. Chiang, “Speed Superiority of Scaled Double-Gate CMOS,” IEEE Trans. Electron Devices, vol. 49, pp. 808-811, May 2002.
- V. P. Trivedi and J. G. Fossum, “Scaling Fully Depleted SOI CMOS,” IEEE Trans. Electron Devices, vol. 50, pp. 2095-2103, Oct. 2003.
- V. P. Trivedi, J. G. Fossum, and A. Vandooren, “Non-Classical CMOS Device Design,” Proc. IEEE Internat. SOI Conf., pp. 155-157, Oct. 2003.
- J. G. Fossum, M. Chowdhury, V. P. Trivedi, T.-J. King, Y.-K. Choi, J. An, and B. Yu, “Physical Insights on Design and Modeling of Nanoscale FinFETs,” Tech. Dig. 2003 Internat. Electron Devices Meeting, pp. 679-682, Dec. 2003.
- J. G. Fossum, J.-W. Yang, and V. P. Trivedi, “Suppression of Corner Effects in Triple-Gate MOSFETs,” IEEE Electron Device Lett., vol. 24, pp. 745-747, Dec. 2003.
- J. G. Fossum, L. Ge, M.-H. Chiang, V. P. Trivedi, M. M. Chowdhury, L. Mathew, G. O.Workman, and B-Y. Nguyen, “A Process/Physics-Based Compact Model for Nonclassical CMOS Device and Circuit Design,” Solid-State Electron., vol. 48, pp. 919-926, June 2004.
- J.-W. Yang and J. G. Fossum, “Infeasibility of Nanoscale Tri-Gate CMOS Transistors,” submitted to IEEE Trans. Electron Devices, Feb. 2004.
- V. P. Trivedi, J. G. Fossum, and M. M. Chowdhury, “Nanoscale FinFETs with Gate-Source/Drain Underlap,” submitted to IEEE Trans. Electron Devices, Apr. 2004.

Nanoscale Multi-Gate MOSFETs

A suite of device-simulation tools, including a generic physics/process-based compact model for double-gate (DG) MOSFETs (UFDG in Spice), is used to convey physical insights on nanoscale multi-gate MOSFETs. For DG CMOS, short-channel effects, carrier-energy quantization effects, and performance projections are discussed. The DG FinFET, which is attracting most attention now, is emphasized by the revelation of unique design and modeling issues it presents. Undoped fins and metal gates will be needed, for which the concept of gate-source/drain underlap in optimal design is explained and assessed. Tri-gate MOSFETs are overviewed and shown to be infeasible for nanoscale CMOS applications. The insights conveyed give added motivation as well as preliminary guidance for the optimal design of nonclassical CMOS scaled to the end of the SIA International Technology Roadmap for Semiconductors where gate lengths are projected to be ~10nm.

Advanced modeling & simulation

Toward decananometer CMOS: modelling challenges
• Quantum confinement (i.e. channel confinement)
• Quantum penetration (i.e. leakage current )
• Non-equilibrium transport (hot carriers, ballistic, etc.)
• Granularity (i.e. fluctuation effects)
• Reliability (e.g. Sio2 vs. High-K)
• Ultimate limits (e.g. S/D tunneling)

Simulation methods and tools
- Electrostatic and Electrodynamics in mesoscopic devices: the role of Schroedinger and Boltzmann equations.
- Validity of the Boltzmann transport equation.
- Models for carrier transport:
• Macroscopic models (drift-diffusion, hydro-dynamic...)
• Monte Carlo (BTE solver, numerical challenges...)
• Quantum transport:
• Ballistic transport
• Monte Carlo with Quantum Corrections
• Full Quantum (Wave Propagation + scattering)
• Device simulation tools: critical issues in “ad hoc” Monte Carlo tools for MOSFETs

Applications
- Inversion layer mobility :
• Ultra thin silicon (SOI)
• Remote Coulomb scattering (thin dielectrics)
- Gate current
- Drain current: the role of scattering and the ballistic limit
- Performance evaluation and comparison of decanano MOSFETS: Bulk, SG-SOI, DG-SOI

Recommended Readings
- Fundamentals of modern VLSI devices, Yuan Taur and Tah K. Ning
- Fundamentals of carrier Transport, II edition, Mark Lundstrom
- Frontiers on Silicon-on-Insulator, George K. Cellar, Sorin Cristoloveanu, Journal of Applied Physic, May 2003

Advanced SOI Characterization Techniques

This tutorial will present advanced techniques for the characterization of the deep taps, interface states, and recombination and generation lifetimes in SOI. The set of these measurements is uniquely appropriate for the characterization of both the silicon film and film/buried oxide interface, and the results provide a comprehensive understanding of the SOI quality. Moreover, these measurements can be used to monitor the fabrication process and the device reliability. At the heart of these techniques is the theory of capture and emission of carriers by deep traps, and the SRH theory of the carrier generation-recombination processes, which may be gainfully reviewed before the tutorial.

Recommended Readings
- D.K. Schroder, «Semiconductor Material and Device Characterization», Wiley (1998).
- E. Takeda, C.Y. Yang, and A.M. Miura-Hamada, «Hot-Carrier Effects in MOS Devices,» Academic Press, 1995.
- T.P. Ma and P.V. Dressendorfer, «Ionizing Radiation Effects in MOS Devices and Circuits,» Wiley, 1989.
- S. Cristoloveanu and S.S. Li, «Electrical Characterization of Silicon-on-Insulator Materials and Devices,» Kluwer, 1995
- J.P. Colinge, «Silicon on Insulator Technology: Materials to VLSI,» Kluwer, 2004

Papers on Characterization
- P.K. McLarty, D.E. Ioannou, and J. P. Colinge, «Bulk Traps in Ultrathin SIMOX MOSFETs by Current DLTS,» IEEE Electron Device Lett., EDL 9, 545 (1988).
- X. Zhao and D. E. Ioannou, «Gated-Diode in SOI MOSFET’s: a sensitive tool for characterizing the buried Si/SiO2 interface,» IEEE Trans. on Electron Devices, 48, 685 (2001).
- T. Ouisse, T. Elewa, S. Cristoloveanu, H. Haddara, G. Borel, and D.E. Ioannou, «Adaptation of the Charge Pumping Technique to Gated P I N Diodes Fabricated on Silicon on Insulator», IEEE Transactions on Electron Devices, ED 38, 1432 (1991).
- D.E. Ioannou, S. Cristoloveanu, M. Mukherjee, and B. Mazhari, «Characterization of Carrier Generation in Enhancement Mode SOI MOSFET’s», IEEE Electron Device Lett., 11, 409 (1990)
- S.P. Sinha, A. Zaleski, and D.E. Ioannou, «Investigation of Carrier Generation in FD Enhancement and Accumulation Mode SOI MOSFET’s,» IEEE Trans. on Electron Devices, 41, 2413 (1994).
- D. Munteanu and S. Cristoloveanu, «Model of Extraction of the Recombination Lifetime in Partially Depleted SOI MOSFET’s,» Microelectronics Engineering vol. 48, 355, (1999).

Reliability

This tutorial will be on the hot carrier and radiation reliability of SOI devices. The presence of two gates in these structures, the nature of the buried oxide, and the possibility of PD and FD device operation make the situation here considerably more complicated than in bulk devices. Of particular interest is the possibility that stressing one channel may in fact cause actual damage on the opposite channel. Indeed, it emerges that this type of injection, which in a broader sense can be viewed as another aspect of channel coupling, has important consequences on the hot carrier device reliability, and if unchecked it is a serious, additional reliability concern for SOI technology. However, it may also be exploited as a new characterization tool or in the design of new devices (for example flash memory).

Recommended Readings
- D. E. Ioannou, F. L. Duan, S. P. Sinha, and A. Zaleski, «Opposite-Channel-Based Injection of Hot-Carriers in SOI MOSFETs: Physics and Applications», IEEE Transactions on Electron Devices, Vol. 45, 1147, May 1998.
- S.P. Sinha, A. Zaleski, D.E. Ioannou, G.J. Campisi, and H.L. Hughes, «Hot Hole Induced Interface State Generation and Annihilation in SOI MOSFET’s,» IEEE Elect. Dev. Letters, 17, 121 (1996).
- S. Cristoloveanu, S.M. Gulwadi, D.E. Ioannou, G.J. Campisi, and H.L. Hughes, «Hot Carrier Induced Degradation of Front and Back Interfaces in PD and FD SIMOX MOSFET’s,» IEEE Electron Device Letters, 13, 603 (1992).
- R.K. Lawrence, D.E. Ioannou, H.L. Hughes, P.J. McMar, and B.J. Mirtik, «Charge Trapping Versus Buried Oxide Thickness for SIMOX Structures», IEEE Trans. Nuc. Sci. 42, 2114 (1995).
- R. K. Lawrence, and D.E. Ioannou, «Electron Traps on High-Temperature Oxidized SIMOX Buried Oxides,» IEEE Electron Device Letters, 17, 341 (1996).
- O. Musseau, «Single Event Effects in SOI Technologies and Devices,» IEEE Trans. Nuc. Sci. 43, 603 (1996).

Low- and high-temperature operation

SOI MOSFETs have lower leakage currents than bulk devices at high temperature, as well as a smaller variation of threshold voltage with temperature. They are also immune to temperature-induced latchup. As a result, SOI circuits can operate at temperatures above 300oC, while bulk CMOS is usually limited to 150oC. Low-temperature operation improves mobility and subthreshold slope, but, more importantly, opens the possibility of exploring quantum effects. Subband splitting can be observed in two- and one-dimensional SOI devices, and single-electron transistors operation is made possible.

Recommended Readings
-
«Low temperature electronics: from fundamental physics to emerging silicon technologies», C. Claeys and E. Simoen, Electrochemical Society Proceedings, Vol. 2003-09, Ed. by. J.A. Martino, M.A. Pavanello and N. I. Morimoto, pp. 96-11, 2003;
- Device and Circuit Cryogenic Operation for Low Temperature Electronics: http://www.wkap.nl/prod/b/0-7923-7377-4

High-temperature operation:
UCL: http://www.dice.ucl.ac.be/soi/activities/hightemp.html
Cissoid: http://www.cissoid.com/index.2.html
Honeywell: http://www.ssec.honeywell.com/hightemp/

Device Characterisation and Analogue Design Styles for SOI CMOS

This talk will present issues important for the analogue designer when using SOI CMOS. We will start with a review of some of the device behaviour which gives SOI devices a unique character, and examine how the small signal and large signal characteristics affect its application in simple analogue circuit functions. We will also address how modelling for circuit simulation must also account for the special problems. We will then proceed to consider some circuit design styles particularly suited to the technology, where we aim to handle any potential problems, and also to exploit the advantages inherent in SOI. Specific design examples will be presented and analysed, covering data conversion mixed signal and very high frequency communications.

Design for SOI digital circuits

This lecture aims at providing a complete understanding of the design issues with partially-depleted SOI CMOS technologies. After an introduction to the SOI partially-depleted transistor and its electrical behavior, all the different aspects when dealing with the design of digital circuits will be reviewed including Spice modeling, design of digital and I/O cells and SRAM design. A special attention will be paid to the advantages brought by SOI and the design challenges as a counter part.

Recommended Readings
- "CMOS circuit design, layout, and simulation", R. J. Baker, H. W. Li, D. E. Boyce, IEEE Press Series on Microelectronic Systems, S. K. Tewksbury, Series Editor
- "SOI circuit design concepts", K. Bernstein, N. J. Rohrer, Kluwer Academic Publishers
- "SOI design: analog, memory and digital techniques", A. Marshall, S. Natarajan, Kluwer Academic Publishers


Design for SOI-RF circuits

This talk aims to demonstrate the potential of the Partially Depleted (PD) CMOS SOI technology for RF applications. After a brief introduction on silicon technologies challenges for RF integration, a comparative study between CMOS SOI, and classical CMOS bulk and BiCMOS technologies for high performances mixed signal circuits is given in the first part of the presentation. This study shows the main SOI advantages over bulk but at the same time highlighting the specific phenomena affecting SOI, as floating body and self-heating, witch should be taken into account for a successful design. Moreover, technological issues are addressed in order to better understand the effects of technological trends as well as process optimisation on RF performances. In the second part of this work the design of three RF circuits is presented: an LNA, a mixer and an antenna switch integrated in 0.12μm PD SOI processes. The very good performances measured for the antenna switch and for the LNA are representative of the great potential of SOI in terms of substrate isolation and loss reduction as well as low noise with low power consumption.

Recommended Readings
- A. Marshall, S. Natarajan "SOI design : analogue, memory and digital techniques" Kluwer Academic Publishers.
- Benzad RAZAVI "RF Microelectronics" Prentice Hall (1998) , ISBN: 0-13-887571-5


Design for low-power/low-voltage with SOI
This lecture will explain why SOI CMOS is the best suited technology for low-power/low-voltage design for digital and mixed-signal applications. The different solutions to achieve a low-power/low-voltage design will be described, dealing with the different problems that need to be addressed such as leakage current (including gate leakage and off-current) and dynamic power.
SOI for MEMS and Microsensors fabrications
This lecture will cover the industrial use of SOI for sensor fabrication. The lecture will start with a technical introduction on SOI micromachining techniques. Drawbacks and advantages of different techniques will be discussed. In a second part, examples of potential uses of SOI for sensors fabrication will be highlighted. The third part will focus on different industrial MEMs products developed by Tronic’s Microsystems using its Epi-SOI surface micromachining technology. The lecture will end with a quick overview of MEMSOI services, the Europractice consortium for MEMS on SOI.

Recommended Readings
- S Renard, "Industrial MEMS on SOI", Journal of Micromechanics and Microengineering, Vol 10, pp 245-249, 2000
- Convection-based micromachined inclinometer using SOI technology, S. Billat, H. Glosh, M. Kunze, F. Hedrich, J. Fred, J. Auber, W. Lang, H. Sandmaier, W. Winner, MEMS 2000, p 159, (0-7803-5998-4/01/$10.00 ©2001 IEEE)
- Bulk micromachining of SOI wafers using double sided lithography and anisotropic wet etching, Henrik Rodjegard, Gert Anderson - Micromachining and Microfabrication 2000 - Proceedings of SPIE Vol. 4174 (2000) p 485
- A high performance silicon micro-pump for disposable drug delivery systems, Didier Maillefer, Stephan Gamper, Béatrics Frehner, Patrick Balmer - MEMS 2001; p. 413 - 417.
- Laterally Moving Bi-Stable MEMS DC-Switch for Biomedical Applications, R.A.M. Receveur, C. Marxer, F. Duport, R. Woering, V. Larik and N.F. de Rooij, 0-7803-8265-X/04/$17.00 ©2004 IEEE
- SOI sensors and epitaxial MEMS, Makoto Ishida, J. Indian. Inst. Sci. Nov-Dec 2001, 81, 619-626 (http://journal.library.iisc.ernet.in/vol200106/paper1/makoto.pdf)


Ultimate Scaling of SOI MOSFETs

At recent CMOS conferences, operational MOS transistors shorter than 10nm have been demonstrated. Yes, but their electrical characteristics remain by far behind the specifications (ITRS Roadmap), therefore menacing the future of the Moore’s laws. We will indicate and analyse the physical causes of this scaling failure, and point out potential solutions. We will show how non-classical device structures (ultra thin single- and double-gate devices such as SOI, FinFET, SON - Silicon On Nothing devices, etc.) and new materials (HK-dielectrics, metallic gates, strained-Si, SiGe heterostructures, Germanium) help to overcome or at least attenuate the problems with short-channel effect, with drain-induced barrier lowering effects, with quantum effects, with discreteness of the matter, with high-field effects, with mobility degradation, with subthreshold leakage etc., etc. Consequently, how these new features will allow retrieving HEALTHY scaling and thus prolong the Moore’s laws upto the end of the Roadmap, and even more, project CMOS to the Nano-world. In this perspective, we will also benchmark ultra-thin body CMOS against other devices and try to show that even in the scale of a few nanometers, UTB devices can provide a powerful and industrially viable solution. In order to become reality, this huge potential of UTB CMOS requires optimisation based on a good understanding of the physics of these devices. We will analyse the latter in terms of optimal Silicon film thickness, optimal BOX thickness, Ground-Plane operation, channel doping, threshold voltage adjustment etc. etc. Finally, the UTB devices roadmap will be proposed.

Recommended Readings
-
Chapitre 3 (Introduction à la physique du transistor MOS) dans "Physique des dispositifs pour circuits intégrés silicium" série EGEM (Electronique-génie électrique-microsystèmes) sous l'édition de J. Gautier, Hermes, Lavoisier 2003
- Chapter " NonClassical CMOS " in section ERD (emerging research devices) of ITRS 2003, available on the web.


Strained Si on SOI MOSFET

Strained Silicon on Insulator substrates combine the advantages of strained channels in terms of carrier transport and mobility with the advantages of SOI-like architectures in terms of current control and reduction of short channel effects. This lecture has the objective of presenting the challenges associated with the development of this technology, with the different techniques presently under study to realize the substrates. The eventuality of a strain relaxation during device fabrication will be addressed. Finally, a state-of-the art of preliminary results obtained on strained Si on Insulator MOSFETs will be presented together with further prospects.
Quantum effects in SOI devices

In this lecture, I will review some spectacular effects of quantum mechanics and of charge quantization in small SOI devices. A better understanding of these effects , which emerge mostly at low temperature, is prerequisite for a vision of future devices at the end of the roadmap. In particular the distance between the field effect transistor and the single electron transistor will decrease as the size of the device, with a very large impact of the source-drain architecture. Also the quantum interference phenomena in conjunction with the residual static disorder existing in small SOI devices will affect strongly the sample-to-sample dispersion. How robust are these quantum effects (charge and energy quantization, multiple quantum coherent diffusions, resonant tunnelling,.) at room temperature in very small devices is a major open issue, we will address in conclusion.